Thesis
Title Realisation of III-V Tunnel-FET with in-situ ultimate scaled gate stack for high performance power efficient CMOS / by Yen-Chun Fu.
Author Fu, Yen-Chun, author.
Production [Glasgow] : University of Glasgow, 2017.

Status Loan Type Location Shelf-mark
 Reference Only  Not for loan  Library Research Annexe  Thesis TA5022  
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Description 152 pages : illustrations (chiefly colour) ; 30 cm
Note A thesis submitted for the degree of Doctor of Philosophy to the Department of Electronics and Electrical Engineering, School of Engineering, University of Glasgow, September 2017.
Thesis Ph.D. University of Glasgow 2018 School of Engineering, Electronics and Nanoscale Engineering.
Bibliography Includes bibliographical references.
Note Electronic version also available via Enlighten : Theses http://theses.gla.ac.uk/30588/
Library Class Thesis TA5022
Subject Metal oxide semiconductors -- Theses PhD.
Field-effect transistors -- Theses PhD.
Indium phosphide -- Theses PhD.
Electronic circuits -- Theses PhD.
Nanoelectronics -- Theses PhD.
Other Author University of Glasgow, degree granting institution.

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