Thesis
Title Validation and verification of the interconnection of hardware intellectual property blocks for FPGA-based packet processing systems / Paul Edward McKechnie.
Author McKechnie, Paul Edward.
Published 2010.

Status Loan Type Location Shelf-mark
 Reference Only  Not for loan  Library Research Annexe  Thesis TA0977  
 NOT KNOWN  Not known  SLI Institute  Thesis TA0977 c.2
More Details
Description xix, 187 p. : ill. ; 30 cm.
Note Eng.D. thesis submitted to the Faculty of Engineering, Department of Electronics and Electrical Engineering, the Universities of Glasgow, Edinburgh, Heriot Watt, Strathclyde, for the degree of Doctor of Engineering in System Level Integration, 2010.
Thesis Thesis (Eng.D.) -- University of Glasgow, 2010.
Bibliography Includes bibliographical references (p. 174-187).
Note Electronic version also available via Enlighten: Theses, http://theses.gla.ac.uk
Library Class Thesis TA0977
Subject Intellectual property -- Theses EngD.
Field programmable gate arrays -- Theses EngD.
Packet switching (Data transmission) -- Theses EngD.
Computer network protocols -- Theses EngD.

Permanent link to record