Thesis
Title Design and modelling of clock and data recovery integrated circuit in 130 nm CMOS technology for 10 Gb/s serial data communications / Maher Assaad.
Author Assaad, Maher.
Published 2009.

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 Reference Only  Not for loan  Library Research Annexe  Thesis TA0458  
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Description viii, 130 p. : ill. ; 30 cm.
Note Ph.D. thesis submitted to the Department of Electronics and Electrical Engineering, Faculty of Engineering, University of Glasgow, 2009.
Thesis Thesis (Ph.D.) - University of Glasgow, 2009.
Bibliography Includes bibliographical references.
Note Electronic version also available via Enlighten: Theses, http://theses.gla.ac.uk
Library Class Thesis TA0458
Subject Integrated circuits -- Theses PhD.
Metal oxide semiconductors, Complementary -- Theses PhD.
Metal oxide semiconductor field-effect transistors -- Theses PhD.
Data communication systems -- Theses PhD.

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